1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, to a semiconductor chip which can provide an improved alignment precision when stacking semiconductor chips, thereby being suitable for preventing the occurrence of a poor connection between semiconductor chips, and a stacked semiconductor package having the same.
2. Description of the Related Art
Packaging technologies for a semiconductor device have been continuously developed according to demands toward miniaturization and high capacity, and recently, various technologies for a stacked semiconductor package capable of satisfying miniaturization, high capacity and mounting efficiency are being developed.
The term “stack” that is referred to in the semiconductor industry means a technology of vertically piling at least two semiconductor chips or semiconductor packages. In the case of a memory device, by using a stacking technology, it is possible to realize a product having memory capacity larger than that obtainable through semiconductor integration processes and improve mounting area utilization efficiency.
Among stacked semiconductor packages, a stacked semiconductor package using through electrodes has a structure in which through electrodes are formed in semiconductor chips and the semiconductor chips are stacked in such a way as to be electrically connected through the through electrodes. In the stacked semiconductor package using the through electrodes, since electrical connections are formed through the through electrodes, advantages are provided in that an operation speed can be improved and miniaturization is possible.
In the stacked semiconductor package using such through electrodes, if a misalignment occurs between stacked semiconductor chips, the positions of the through electrodes of an upwardly positioned semiconductor chip and the through electrodes of a downwardly positioned semiconductor chip are not aligned with each other, by which a poor connection occurs. Further, the occurrence of a poor connection becomes serious as the pitch of the through electrodes decreases by an influence of high integration.